Job Description

Must possess hands on experience in P&R from RTL to GDS including timing closure and Physical verification.Must have experience with latest technology nodes Design experience in all aspects of physical design. Synthesis, Floorplan, P&R, CRS, Timing Closure etc. Proficient with Synopsys & Cadence EDA tools associated with the role. Experience in Mentor Calibre tools to run Physical verification Experience in Tcl/Tk, PERL, Make file is a Plus Excellent verbal and written communication skill is required.

Job Description

Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at-speed testing, I/O testing requirements, MBIST and Repair, Implement Test Logic.
Generate and debug test patterns Exposure to EDA tools viz. DC,LogicVision, Fastscan, Tetramax Good knowledge about all DFT concepts& ATPG Flow.
Vector Generation, ATPG Pattern Generation, Validation, Scan insertion and validation, Timing Analysis Chip-level DFT insertion with sound knowledge of scan compression, MBIST & JTAG techniques.
Should have good post silicon DFT bringup and debug experience. Hands on in multi-vendor DFT tools. Create test plan for complex ASICs and drive the DFT implementation & verification. Ability to guide people, multiplex many issues and set priorities. Good communication and leadership skills

Requirements

Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
Experience in formal verification with Cadence LEC
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in RTL HDL languages Verilog/VHDL Understanding of RTL to GDS flow
Previous experience in QC flow is a plus

Expertise in Perl, TCL language is a plus

Requirements

Expertise in AUTOSAR Standard, Architecture, Good in In-Vehicle Infotainment, Connectivity.
Work Experiences with Infineon TriCore and ARM Cortex M3, or Renesas V850 family
Good knowledge of RTOS (i.e., ThreadX, WinCE, QNX )
Good understanding of Advanced Driver Safety Applications, Proficiency in Automotive Protocols – CAN, Flexray, LIN.
Hands on experience in I2C, SPI, UART.
Work experience with using tools like CANOe, CANanalyser is a plus.
Experiences with CMMI or ASPICE development process
Strong in Prototype and production diagnostics
Good Knowledge of software configuration management concepts and tools (Clearcase, Subversion).

Good Communication skills and desire to work as a team player is must.

Job Responsibilities

Requirement
Software Architecture: AUTOSAR MCAL, OS, AUTOSAR Stack.
Networking and communications protocols (CAN, LIN, Ethernet, FR).
Experienced in microcontrollers (Freescale, ST, Renasas, etc. both single and Multi core micros).
RTOS and Embedded Systems. Good problem solving ability and analytical skills.

Experience in design and testing of automotive diagnostic protocols
Hands-on experience in the design, implementation and testing of Automotive Serial Communication Protocol (CAN / LIN / Ethernet ) in embedded Systems
Programming skills in VB and/or C++.
Exposure to Usage of CAN Tools (e.g. CANoe with LIN, CANalyzer, NeoVI)

Preferred Skills

Experience in Architecture layers / Methodology / Autosar Tools, pertinent to Communication Protocol, Autonomous architecture
Knowledge in CAN HW and SW related parameters used for Calibration/Configuration
Knowledge in protocol conformance documentation and testing
Communication and Inter-personal Skills
Ability to work in a global team environment

Preferred Skills

Strong knowledge on UDS Diagnostics
Creating Bootloader Releases.
Strong Embedded C knowledge
CAPL scripting, CANoe/CANalyzer tools
SW development life cycle
Automotive development

Preferred Skills

Expertise in Linux device drivers
Good knowledge of Linux kernel and BSP
Good understanding of ARM based SOC
Bootloader and Board bring up
Good problem solving skills